This invention relates to a pattern inspection system and, more particularly, to a circuit-pattern inspection system for automatically detecting broken lines and other visual defects of circuit-patterns on a printed wiring circuit board.
For the inspection of patterns such as circuit-patterns on a printed wiring board, there has been proposed and practiced an inspection method on the basis of comparison between two patterns as described in Japanese Patent Publication No. 59-24361. Another proposal is an inspection system which does not require more than one pattern which is under inspection as described in Japanese Patent Unexamined Publication Nos. 53-83768 and 58-125826. Also for the inspection of a single pattern, there is an inspection method which compares the pattern with its design data as described in Japanese Patent Unexamined Publication No. 52-42790. As a method of inspection based on the memory of an actual pattern, there is a proposal in the bulletin of The Institute of Television Engineers of Japan, Vol. 36, No. 1, pp. 38-44, published in 1982, in which two sets of circuit-patterns on the same printed wiring board are compared, but in this case part of one pattern set is memorized temporarily and another pattern set is compared with it. This is a variation of the method based on the comparison of two sets of actual patterns.
Among these conventional techniques, the method of patent publication No. 59-24361 necessitates two patterns for comparison. The inspection system of patent publication Nos. 53-83768 and 58-125826 cannot detect a defective pattern having a close resemblance to a normal pattern. The method of patent publication No. 52-42790 necessitates an elaborate electric circuit for the generation and development of a pattern from design data, and it is formidable to transfer and store a vast amount of data. The inspection method in the above institute bulletin fails in general applicability even though it is effective for limited uses.